Field of Invention
Various embodiments of the present disclosure relate to a digital phase locked loop (PLL) and a method of driving the digital PLL, and more particularly, to a digital PLL and a method of driving the digital PLL, which can minimize spurious noise.
Description of Related Art
A Charge pump phase locked loop (hereinafter referred to as “PLL”) has been chiefly used so as to implement a radio frequency (RF) synthesizer for multi-band mobile communication. Such a charge pump PLL is implemented as an analog circuit.
When a charge pump PLL is implemented as an analog circuit, a separate analog/RF library is required in addition to a design library, which is provided by a standard digital CMOS manufacturing process, due to the signal characteristics of the analog circuit. Therefore, it is difficult to integrate the charge pump PLL, implemented as an analog circuit, with a digital baseband signal processing block that uses a digital CMOS manufacturing process.
Further, with the development of recent manufacturing process technology, a nanometer scale digital CMOS manufacturing process has been developed, and thus a digital baseband signal processing block has been developed using a nanoscale digital CMOS manufacturing process.
Meanwhile, a digital circuit is hardly re-designed and may be implemented to be easily adapted to a manufacturing process technology. However, an analog circuit must be re-designed whenever manufacturing process technology is changed. Further, as CMOS manufacturing process technology is developed to nanoscale technology, an operating voltage is decreased, and thus it is difficult to apply an analog circuit to CMOS manufacturing technology.
Therefore, research into and development of technology for implementing an analog PLL as a digital PLL has been actively conducted. However, a digital PLL includes spurious noise, by which speech quality is deteriorated.